So called “3D” or “2.5D” semiconductor device integration technology, which uses a through-silicon via (TSV), is getting attention for the possibility of achieving greater device (integrated circuit) functionality and the like.
In the integration technology using a TSV, a solder bump (also called a through electrode) may be formed on both the upper and lower surfaces of a chip/die. The bump on the lower surface side of the chip/die is typically formed while the upper surface side of the chip/die (which typically the side on which circuit components are formed which the chip/die is in a wafer state) is adhered to a supporting substrate. To bond the upper surface of the chip/die (while in a wafer state) and the supporting substrate together, an adhesive, for example, is used. Often a bump or protrusion (to be used to subsequently join the chip/die to another element) will also be formed on the upper surface of the chip/die before the support substrate is adhered to the wafer. Moreover, before the formation of the bump on the lower surface side of the wafer, the wafer is sometimes first ground to make the wafer thinner.
As described above, since the lower surface side of the wafer is machined (e.g., subjected to grinding to reduce overall wafer thickness) in this 3D and 2.5D integration technology, bonding between the upper surface of the wafer and the supporting substrate is required to have high strength to prevent a bonding breakdown at the time of machining of the lower surface side of the wafer. However, depending on the height of bump or protrusion on the upper surface side of the wafer or the shape of the element structure, adequate bonding strength sometimes cannot be obtained.